1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits that use metal-oxide-semiconductor (MOS) transistors, has been increasing. With the increase in the degree of integration, MOS transistors used in the integrated circuits have been miniaturized to the nanometer scale. With such a miniaturization of MOS transistors, there may be a problem in that it becomes difficult to suppress a leakage current and the area occupied by circuits is not easily decreased from the viewpoint of securing a required amount of current. In order to address this problem, a surrounding gate transistor (hereinafter referred to as an “SGT”) has been proposed in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
In an existing inverter that uses an SGT, one transistor is formed in a single silicon pillar, and an nMOS transistor formed of a single silicon pillar and a pMOS transistor formed of a single silicon pillar are formed on a plane (refer to, for example, Japanese Unexamined Patent Application Publication No. 2008-300558). Since at least two silicon pillars are formed on a plane, an area corresponding to the at least two silicon pillars is necessary.
In an existing non-volatile memory, a plurality of gates are formed around a single silicon pillar (refer to, for example, Japanese Unexamined Patent Application Publication No. 2014-57068). A gate insulating film is formed on a side wall of a silicon pillar, and a source line and a bit line are connected at an upper end and a lower end of the silicon pillar.